ASML Eyes 40% High-NA Productivity Boost With 12-Inch Masks

ASML and TSMC have launched an industry initiative to move High-NA EUV lithography toward larger photomasks, targeting a 12-inch mask pilot line in 2031 and lithography-system readiness for advanced-node production in 2033. Samsung has joined the initiative, while Intel has separately said it has been working on large-format-mask readiness with ASML and suppliers for several years.

The operating cost and capacity target is now quantifiable. ASML chief technology officer Marco Pieters told Reuters that a successful move to the larger format could raise the productivity of High-NA systems by about 40%. That is the useful number for semiconductor investors because High-NA scanners are entering manufacturing years before the larger mask arrives: Intel says it is already using High-NA on selected Panther Lake production layers, Samsung plans DRAM high-volume manufacturing in 2028 and TSMC says advanced-node high-volume use starts in 2030.

The 12-inch programme is therefore a utilization and cost upgrade to an installed and growing High-NA base. With today's 6-inch masks, High-NA's anamorphic optics expose a smaller field than conventional EUV. Large dies can require two fields to be patterned and stitched. A larger mask is intended to restore a full field for large data-center chips, remove stitching constraints and increase wafer throughput.

The return comes from more output per expensive scanner

High-NA improves resolution by raising numerical aperture, but the optical design trades away exposure-field size when the industry keeps the legacy mask format. That trade is manageable for smaller dies and for layers where stitching is acceptable. It becomes more expensive as customers use High-NA on more layers and as AI processors approach the reticle-size limits of today's advanced lithography.

TSMC's roadmap makes the timing important. The foundry expects High-NA layer count to rise as transistor structures become more complex, particularly for AI applications. Larger masks arriving in the early 2030s would therefore address a productivity penalty just as the installed High-NA fleet and number of High-NA process steps are expected to be larger.

The migration is broader than a scanner modification. Mask writers, inspection and metrology equipment, handling systems, automation, pellicles and fab logistics all need to support the larger substrate. That creates equipment-development work across the mask ecosystem, although today's public record gives no defensible dollar capex pool or supplier-by-supplier revenue allocation. Calling it a quantified new equipment cycle would run ahead of the evidence.

The investment conclusion is narrower and stronger. High-NA adoption is already moving forward with 6-inch masks, so the 2033 date is not a delay to the technology. The 12-inch initiative is ASML's attempt to improve the economics of the installed tool by as much as 40% through higher productivity and full-field patterning. If that gain is realized, it raises the value of each very expensive High-NA scanner and makes deployment on more layers easier to justify; the beneficiaries beyond ASML will depend on which mask-tool and handling suppliers win the multi-year qualification work.

Sources

• ASML and TSMC initiative, Sept. 8, 2026: https://www.globenewswire.com/news-release/2026/09/08/3357321/0/en/asml-and-tsmc-announce-initiative-to-pioneer-industry-transition-to-large-format-photomasks-for-high-na-euv.html
• Intel Foundry and ASML High-NA update, Sept. 7, 2026: https://www.intel.com/content/www/us/en/newsroom/news/intel-foundry/intel-foundry-asml-accelerate-industry-readiness-for-high-na-euv.html
• Samsung and ASML collaboration, Sept. 8, 2026: https://news.samsung.com/global/samsung-electronics-and-asml-expand-strategic-collaboration-for-next-generation-semiconductor-manufacturing
• Reuters, Sept. 8, 2026: https://www.moneycontrol.com/news/business/asml-to-work-with-major-chipmakers-to-use-latest-tools-for-larger-chips-14025026.html