CAS reports 13ns switching and 19-million-to-1 read contrast in a 64-cell ferroelectric array

Researchers at the Chinese Academy of Sciences' Institute of Semiconductors have demonstrated a sliding-ferroelectric tunnelling junction with a 1.9x10^7 resistance ratio at a 0.5-volt read voltage, endurance beyond 10^11 switching cycles, reliable switching with a 13-nanosecond pulse and switching energy of 6.5 femtojoules per bit. The work, published in Science, also includes an 8-by-8 array in which all 64 cells displayed bistable behavior.

The institute reports an on-state current density of 222 A/cm² and says the tunnelling resistance ratio is more than four orders of magnitude higher than in previously reported sliding-ferroelectric tunnelling junctions. That benchmark is more informative than the raw 1.9x10^7 figure alone: it shows how far the reported read contrast moved the frontier within the same device class.

The result matters because the metrics arrive together. New nonvolatile memories often improve one property by sacrificing another: a large read window may come with high write energy, a fast switch with poor endurance, or an elegant single device with too much variation to form an array. The CAS result reports wide read contrast, low intrinsic switching energy, high cycle life, high read current and nanosecond operation in the same device family.

The junction uses atomically thin two-dimensional materials whose relative layer displacement changes ferroelectric polarization and therefore the tunnelling barrier. The stored state is read electrically as a large resistance difference, giving circuit designers a potentially strong state-discrimination margin in an extremely thin active region.

The paper clears a device trade-off, not a manufacturing one

The 64-cell demonstration is an important step beyond a single junction because it tests whether bistability survives integration across a small array. It is still many orders of magnitude away from a commercial memory macro. Retention across temperature, cell-to-cell variation, selector behavior, defect density, interconnect parasitics and peripheral sensing become progressively more difficult as arrays scale.

The 6.5 fJ/bit figure covers device-switching energy. A usable memory consumes additional energy in drivers, addressing, sense amplifiers, data movement and error correction. Strong device physics can therefore lose part of its advantage when measured at the macro or system level.

That boundary is especially important for compute-in-memory claims. Bringing storage and some computation closer together can reduce data-movement energy, but a 64-cell array does not establish an end-to-end accelerator, memory hierarchy or commercial compute-in-memory system. It establishes a device candidate with unusually favorable intrinsic properties.

Manufacturing is now the economically decisive hurdle. Two-dimensional stacks can be assembled with material quality and layer alignment in a laboratory that are difficult to reproduce across wafers. A commercial process would need scalable deposition or transfer, CMOS-compatible thermal budgets, tight interface control, high yield and a cost competitive with incumbent nonvolatile memories.

The Science paper clears several physics-level objections, but manufacturing remains unresolved. A substantially larger array fabricated with a repeatable wafer-scale process, with full peripheral-energy and retention data, would show whether the four-orders-of-magnitude device advantage survives the transition from exceptional experiment to useful memory technology.

Sources

• Chinese Academy of Sciences, Institute of Semiconductors, September 11, 2026: https://www.semi.ac.cn/xwdt/zhxw/202609/t20260911_8280688.html
• Science paper: https://www.science.org/doi/10.1126/science.aeh3697