
Qualcomm's 18x memory estimate comes from a two-layer test stack
Qualcomm's 18x memory estimate comes from a two-layer test stack
Qualcomm's new 18x estimate uses measurements from a two-layer DRAM stack, half the four layers planned for shipping products, against published LPDDR5X specifications. AI250 card sampling is due in the first half of 2027.
The two 18x claims use different comparisons
Qualcomm reports first silicon tests for High Bandwidth Compute memory, or HBC, and an estimated 18x comparison. It does not validate June's 18x AI250 card goal against AI200.
In its June Investor Day release, Qualcomm said that AI250 "is designed to enable an industry-leading 133 TB/s per card, an 18x increase in effective memory bandwidth compared to AI200 with LPDDR5X".
Qualcomm's product page gives 7.4 PB/s of effective bandwidth per AI250 rack and 414 TB/s of memory bandwidth per AI200 rack. Both racks list 38.6 TB of memory. In the same units those figures give about 18x. That checks the rack specifications, which define bandwidth differently. It does not confirm the 133 TB/s card goal or November's estimate.
What the November test covers
In a company blog post, Rashid Attar, Qualcomm senior vice president of engineering, said first generation silicon "validated the full memory read-write path and near-memory computations at production-representative dimensions". Tests ran on automated equipment using randomised weights and activations, not an AI model. They therefore cannot establish inference throughput or tokens per dollar.
Qualcomm's table estimates effective memory bandwidth "18x higher than LPDDR5X" and bandwidth per watt "more than 5x higher than HBM4". LPDDR5X is the low-power memory in AI200; HBM4 is the stacked memory used in the fastest GPUs. Neither comparison is a measured AI250 card result. No absolute bandwidth or power figure is supplied.
How Qualcomm calculated the estimate
Qualcomm says its estimates use "measured first-generation Qualcomm HBC silicon results normalized to target operating conditions and compared with published competing product specifications". Without raw measurements, operating conditions or a fully specified comparison baseline, the November 18x cannot be reproduced.
ServeTheHome reported that the test stack "just had 2 layers of DRAM dies" and future shipping products "will have 4 layers". It also reported testing in LPDDR5X and HBC modes, but the published 18x comparison is to external specifications, not a measured ratio between those modes.
The missing four layer result cannot be inferred from the two layer result. ServeTheHome described thermal limits as "one of the major technical hurdles"; no thermal results were reported.
Efficiency and progress claims
June's 6x bandwidth per watt goal compared AI250 at card level with HBM. November's more than 5x figure compares a normalised HBC estimate with HBM4. Different scopes, baselines and conditions preclude treating one as evidence for the other.
Qualcomm also reports a qualified wafer to wafer bonding process and built in redundancy. It says a data center product "has taped out" and that early bring up of bonded DRAM tiers "is yielding today". These milestones do not establish production yield or manufacturing cost.
CTOL view and the indicator to track
In CTOL's view, identical advertised rack memory capacity and approximately 18x higher claimed effective bandwidth describe a difference in design. They do not demonstrate a gain in actual inference throughput. The evidence supports a narrower finding: Qualcomm reports working memory functions in a two layer test stack, using estimates for its headline ratios.
CTOL sees three possible outcomes:
- Most likely: the 4 November results add development status, not a measured AI250 card benchmark, consistent with sampling due in the first half of 2027.
- Plausible: four layer and thermal results appear by sampling, testing whether the intended stack works without yet validating card performance.
- Unlikely: the 4 November results already include a comparable measured AI250 card result.
CTOL's moderate confidence call is that the 4 November fiscal fourth quarter disclosure will not establish the 133 TB/s per card target. A disclosed AI250 card measurement of 133 TB/s under specified conditions would falsify it; the 18x comparison also needs a matched baseline. Four layer stack tests alone would not.